In high performance flash memory architectures, performance is maximized by operating system resources as efficiently as possible. Conventional systems attempt to improve efficiency by allowing multiple operations to be worked on independently through the use of queues, pipelines, and parallel operations. However, when resources in such systems are poorly scheduled, these systems may exhibit a “slinky effect,” such that a system bottleneck moves from one resource to another over time. For example, in a NAND system, a NAND bus interface may be a short-term bottleneck when data are transferred to sets of idle NAND dies. Once the dies begin programming, the NAND bus is idle. Therefore, the idle time on NAND and NAND buses due to poor scheduling leads to poor system performance.